💾 Git Repository: https://github.com/RockPie/SZ_Firmware
¶ Environment
The environment I'm using:
- OS: Microsoft Windows 10 Version 22H2 Build 19045
- Language: Verilog HDL
- Text Editor: Microsoft Visual Studio Code
- Platform: Xilinx Vivado ML Edition 2022.2
¶ Hardware
This project uses an on-board crystal oscillator, an LED, and an external port for test.
¶ Schematics
The related schematic diagram of the LED are introduced in (Smart ZYNQ) a. LEDs and Keys.
The oscillator we use is an active clock source which generates 50 MHz clock signal. And from it we will create many other clock signals.
From this project we are going to start using oscilloscope to monitor our signals. Here we will use one external port on the PCB to show the waveform of a clock signal.
In this example, pin 31 of U13 header is used, which is connected to pin E16 of the FPGA. (Of course you're free to any header pin you like)
¶ Constraints
Apart from our previous constraints, we describe the connection of the external clock signal like:
create_clock -period 20.000 -name sys_clk -waveform {0.000 10.000} [get_ports sys_clk]
set_property PACKAGE_PIN M19 [get_ports sys_clk]
set_property IOSTANDARD LVCMOS33 [get_ports sys_clk]
Here we use create_clock syntax to specify the clock period and duty cycle. A more detailed instruction can be found in 2.3.1.1. Create Clock (create_clock).
Usually we write clock constraints in the front and physical constraints in the back of the .xdc file.
Then we add constraints for the external port.
set_property PACKAGE_PIN E16 [get_ports sys_test_port]
set_property IOSTANDARD LVCMOS33 [get_ports sys_test_port]
set_property SLEW FAST [get_ports sys_test_port]
set_property DRIVE 4 [get_ports sys_test_port]
We can see two new types of constrains occurs. One is set_property SLEW FAST/SLOW and the other is set_property DRIVE 2/4/6/8/12/16/24. These two set the slew rate and driving current (in mA) of the port.
We don't have to specify the slew rate and driving current for each port in the project. Their default value: SLOW and 12 mA is enough in many cases. In the "Test" section, we can see how these values actually change the driving capability of the pin.
And don't forget to comment the unused ports (sys_keys[1:0]).
¶ Firmware
- Create new projectcreate new empty project for smart ZYNQ
- Add files to projectcreate or import files to a project
- "Compile" a projectrun synthesis, implementation, and generate bitstream
¶ Structure
¶ Code
First we create a new wire for the generated 10 MHz clock.
wire clk_10M;
assign sys_test_port = clk_10M;
clk_wiz_0 clk_wiz_0_inst (
.clk_in1(sys_clk),
.clk_out1(clk_10M)
);
¶ Test
¶ Clock Signal
By using a oscilloscope (150 MHz bandwidth, 1 GSP sampling rate.)
¶ Driving capability
We'll dive deeper to see the different effect 4mA or 12mA(default) driving current will have.
- When in 4 mA mode, there is no obvious overshoot. But the Max/Min value is exceeding normal range.
- Driving with 12 mA, the overshoot pulse become servere. This is mainly because the LVCMOS signal is not correctly terminated. In theory, for LVCMOS standard, it should be grounded with a 50 Ohm resistor.
However in our case, it is diresctly monitored via a 10 MOhm probe, which will cause the overshoot.