This guide is based on Xilinx Vivado ML Edition 2022.2
In this article, we will go through the basic sequence of operations to get the "executable" file (.bit file). Please keep in mind that this is a basic tutorial, and there might be tons of errors/warnings emerging during the process.

(1) Synthesis; (2) Implementation; (3) Generating birstream; (4) Programming device;
- To run synthesis, click "Run Synthesis"(1) under "SYNTHESIS" label.
- This new subwindow allows us to change the number of CPU cores used for synthesis.

- After clicking "OK", on the top right corner we can see Vivado is busy running synthesis.

- When finished, we can specify the next task.

- We could click "Run Implementation"(2) under "IMPLEMENTATION" label, or continue from synthesis.
- The same as step 2, we can specify how many cores to use.

- For implementation, Vivado would take longer time to finish.

- When finished, we can also specify the next task.

- Bitstream file (.bit) is the "executable" file for FPGA. To generate it, we can either click "Generate Bitstream"(3) or continue from implementation.
- Again, specify the number of cores.

- Usually, this process is much faster than implementation.

- When finished, we can specify the next task.

- Click "Hardware Manager"(4) or continue from bitstream generation.
- We can click the "Auto Connect" icon from "Hardware" tag, or choose "Open target" to specify how to connect to a device.

- If there is no problem with the connection, we are allowed to program our device. Click "Program device" or right-click the device from the list.

- Normally Vivado can auto-find the corresponding .bit file of the project. We could also specify it manually.

- After clicking "Program", Vivado will start programming our device. In this way, the FPGA will lose the configuration after powering off. If we want it to function after the next powering up, consider programming to the FLASH memory.