This guide is based on Xilinx Vivado ML Edition 2022.2
Open Vivado
Click "Create Project" in "Quick Start"
You'll see the New Project window pops up, then click "Next"
Here you can name your project and specify the project path.
Choose "RTL Project", and we can choose to specify source files later
In this window, we choose the FPGA model for Smart ZYNQ: xc7z020clg484-1. Product Selection Guide has more detailed info about what these letters and numbers mean.
We have filled in all the info needed! In this window, we check if the project is configured as we want, and click "Finish" to leave the rest work to Vivado.